Vortexlink, Inc.

DFT Lead Full Time Opportunity in Saratoga, CA Responsibilities Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG). Proficiency in Synthesis design constraints. ( Ie SDC) Prior experience with Serializers/Deserilizers. Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis, Define and implement OCC. Exposure to advanced DFT techniques like LBIST and streaming preferred. Fluent in RTL level and Gate level simulation. Supervise ATPG generation and achieve high coverage goals for scan scan. Qualifications Knowledge using synthesis, DFT & Simulation CAD tools Familiarity with logic & physical design principles to drive low-power & higher-performance designs Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL Good understanding of device physics and experience in deep sub-micron technologies 7nm or below. Prior Exposure to EMIB architectures and bridge is a plus. Knowledge of Verilog and System Verilog Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated Ability to work well in a team and be productive under aggressive schedules Prior experience of multiple tape out in deep submicron 7nm or below is required. Master's Degree or bachelor's degree in EE with a minimum of 15+ years of experience.

Staff RTL Engineer, Ethernet Full Time opportunity in Saratoga, CA Position Overview We are seeking an RTL Engineer to help define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. The candidate will be part of Design Group responsible for defining, specifying, architecting, executing and productizing leading-edge Networking devices. Responsibilities Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design integration of the Ethernet IO subsystem, including MAC, PCS, and SerDes. Perform RTL coding, conduct code reviews, and debug designs. Work with third-party vendors to procure and integrate the Ethernet block with MAC, PCS, and PHY. Partner with Verification Engineers to define the test plan, execute verification, and understand both serial and parallel mode VIP behavior. Debug the full Ethernet protocol stack. Engage in post-silicon activities such as bring-up, platform validation, characterization, parameter optimization, and final productization. Support the definition of development flows that improve execution efficiency and quality. Collaborate closely with Physical Design, Firmware, and Design Verification teams to ensure successful end-to-end RTL implementation. Qualifications Master's degree in Electrical Engineering (MSEE) with 8-15 years of experience. Proven record of successful tape-outs and productization, preferably in networking devices. Strong understanding of the Ethernet 802.3 protocol, including framing, encoding, and broadcasting/unicasting; familiarity with Ultra Ethernet developments is preferred. Solid knowledge of SerDes fundamentals, including clocking, Decision Feedback Equalization (DFE), CTLE, and initialization. Comprehensive understanding of multiple clock, reset, and power domain design challenges with safe/robust design practices. Experience in refactoring and restructuring designs to address timing and area challenges, including algorithmic and structural design changes. Ability to optimize hardware versus firmware implementations for overall product performance and efficiency. Excellent knowledge of industry-standard tools and best-in-class practices for high-quality design. Prior experience with source synchronous design implementation. Essential knowledge of Ethernet architectures and Layer 2, Layer 3, and Layer 4 networking protocols. Prior experience in integrating a MAC IP with PCS and SerDes PHY, preferably at 100G or higher. Thorough understanding of the ASIC design flow, including requirements for DFT and physical implementation.

Verification Engineer Full Time opportunity in Saratoga, CA Key Responsibilities Specialized Verification Strategy: Develop verification infrastructure and test cases for ASICs in the area of network fabrics, leveraging your extensive experience in networking. Technical Expertise in ASIC Verification: Provide technical leadership in the verification of complex ASIC designs, ensuring compliance with industry standards and project specifications Gate & Timing simulations: collaborate with the team to execute comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out. RTL Coverage Analysis: deliver detailed coverage metrics to assess the thoroughness of the test suite. Offer actionable feedback to design engineers, focusing on identifying gaps and suggesting enhancements to elevate test effectiveness and broaden coverage scope. Quality Assurance and Process Optimization: Uphold the highest standards of verification quality. Initiate and implement process improvements for increased efficiency and effectiveness. Qualifications ME/BE in Electrical Engineering, Computer Engineering, or related field. Experience: A MINIMUM of 8-15 years in ASIC verification in the area of data center networking. Verification Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM/VMM/UVM) with a strong understanding of ASIC Design and Verification flow. Experience with functional coverage, gate/timing/power simulations, constrained random verification and test-plan documentation is required. Technical Skills: Python/Perl/Tcl experience, strong problem solving and debugging skill is a plus. Domain Knowledge: Prior experience with Ethernet and PCIe Protocols, Serial and Parallel VIP verification modes and High speed Serdes is a strong plus. Communication Skills: Exceptional communication abilities, capable of effectively coordinating, and articulating complex technical issues in a clear manner.

Synthesis Engineer Full Time opportunity in Saratoga, CA We are seeking a Synthesis Engineer to help define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities Define and maintain the synthesis flow-including logic and physical synthesis. Develop and manage synthesis design constraints (e.g., SDC). Design and architect top-level and block-level floorplans for multi-chiplet systems and interposers. Collaborate with micro-architects on feasibility studies and performance, power, and area (PPA) tradeoffs. Work with the Design and DFT teams on scan insertion and synthesis implementation steps. Partner with Design Verification to support equivalence checking and functional sign-off. Assist in defining and integrating low-power optimization strategies into the synthesis flow. Qualifications Master's or Bachelor's degree in Electrical Engineering. Minimum 15+ years of relevant experience. Prior experience with multiple tapeouts in deep sub-micron nodes (7nm or below) is required. Proficiency with Cadence Innovus/Genus or Synopsys Fusion Compiler. Strong scripting skills in Unix shell, Perl, Python, and TCL. Deep understanding of CDC/RDC flows and equivalence checking. Familiarity with CAD tools and logic/physical design principles for low-power, high-performance chips. Knowledge of foundation libraries, VT tradeoffs, multi-track library usage, synchronizers, and lock-up latches. Exposure to datapath synthesis, memory compilers, and power optimization. Knowledge of Verilog and SystemVerilog. Understanding of device physics and deep sub-micron technologies. Experience with EMIB architectures and chip-to-chip bridging is a plus.

Senior Visual Designer (UX/UI) Full Time opportunity, Office located in Mountain View, CA (100% remote considered) We are seeking a highly creative and skilled Visual Designer to spearhead a new visual direction and to lead all aspects of visual and motion design strategy for our mobile healthcare app. In this role you will work across the product organization working closely with cross-functional teams and design area leads to bring together refined interaction and visual design. This is a unique opportunity to make a significant impact, shaping the product's look and feel to enhance user engagement, help our members understand their progress through clear, delightful data visualization, and build a stronger emotional connection with our users. You will be responsible for the entire visual design lifecycle, from conceptualizing fresh aesthetic patterns to meticulously crafting design details and ensuring consistency through reusable design components. Key Responsibilities Define and refine a new visual Lead the conceptualization and development of a new modern visual identity unique member base, instilling trust, and aligned to our brand values Elevate the user experience through visuals Design beautiful, intuitive user interfaces that make complex health data easy to understand and member health progress obvious and motivating Craft examples of detailed visual designs to inspire others by keeping current with latest design trends and sensibly applying Produce high-fidelity mockups, visual assets, style guides, and prototypes leveraging thoughtful typography, color, layout, visual assets Explore and apply motion design and elements of delight to increase impact and micro-interactions to increase usability, UI feedback, and Collaborate closely with other designers, product managers, and engineers to create delightful, consistent, and user-validated experiences across mobile and web. Work with cross-functional partners to develop concepts and iterate new ideas and features working directly with internal users to validate Clearly articulate your design rationale and Conduct user research with interaction designers to gain insights into unmet needs, pain points, and behaviors. Use these insights to inform visual design decisions and improve user experiences. Drive a user-first mindset in everything you do, advocating for user needs while balancing business and technical goals. Qualifications Bachelor's degree in design, art, user experience, or a related field. Exceptional visual and graphic design skills. Strong verbal, written, and visual communication skills, as well as a portfolio that demonstrates both user centric visual design for enterprise and consumer products. 5+ years of visual design and UX design experience, with minimum 2-3 years designing user interfaces for healthcare or related products. Expertise in visual design, graphic design, illustration, and typography, design systems, design patterns, and experience with interaction Experience with motion and data visualization design Experience working with consumer-facing mobile experiences and collaborating with clinical teams and workflows strongly preferred Experience designing AI/ML and LLM augmented experiences strongly Ability to communicate clearly with developers and understand the capabilities and constraints of native mobile design. Great eye and passion for visual design, innovative UI, and demonstration of ability to launch the highest quality interactive experiences

Physical Design Engineer Full Time opportunity in Saratoga, CA Key Responsibilities Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. Proficiency in Synthesis design constraints (SDC). Design and Architect Top Level and block Level Floor planning of the entire SoC. Sound Proficiency in either Innovus or Synopsys Fusion Compiler required. Proficiency in synthesis, Floor planning Power Planning and Timing closure are required. Prior experience with large skew optimized clock tree designs like H-Tree preferred. Clock Grid exposure is a plus. Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure. Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA. Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV. Qualifications Master's Degree or bachelor's degree in EE with a minimum of 10+ years of experience. Knowledge using synthesis, place & route, analysis and verification CAD tools. Familiarity with logic & physical design principles to drive low-power & higher-performance designs. Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL. Good understanding of device physics and experience in deep sub-micron technologies 7nm or below. Knowledge of Verilog and System Verilog. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Prior experience of multiple tape-out in deep submicron 7nm or below is required.